Wafer of chips

5nm Chip

Preparing test wafers

Preparing test wafers with 5nm silicon nanosheet transistors

IBM group of researchers, Global Foundries and Samsung created a new transistor design based on a new inventive process that will lead to more speed and power efficiency at a lower cost. The reason for having a smaller size is to power self-driving cars, on-board AI and 5G sensors. Also, the pressure to keep up with Moore’s Law of 1965 needed to move to a new structure and allow for more transistors on one chip. During the fabrication process, these chips are constructed of horizontal FinFET structured layer with silicon nano sheets to create a fourth gate. Sadly, these chips will not meet the market until after the predecessor 7nm process chips do in 2018.

5nm nanosheet transistors

Silicon nanosheet transistors at 5nm

“As we make progress toward commercializing 7nm in 2018 at our Fab 8 manufacturing facility, we are actively pursuing next-generation technologies at 5nm and beyond to maintain technology leadership and enable our customers to produce a smaller, faster, and more cost efficient generation of semiconductors.” – Gary Patton, CTO and Head of Worldwide R&D at GlobalFoundries

FinFET

The last major breakthrough came in 2009 with the creation of FinFET. The first manufacturing of FinFET was in 2012 with the 22nm process (now 7-10nm process).

First use of the 3D structure to control electric current, rather than the 2D ‘planar’ system of years past.

Maximizes the amount of current flow in the on state  and minimizes the amount of leakage in the off state which makes it more efficient.

“Fundamentally, FinFET structure is a single rectangle, with the three sides of a structure covered in gates” – Mukesh Khare, VP of Semiconductor  Research for IBM

Wafer of chips

Wafer of chips with 5nm silicon nanosheet transistors

Images courtesy of IBM

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